Sequential scan techniques are often used to test integrated circuits. According to a typical sequential scan technique, integrated circuits are designed to operate in functional mode or test mode. In functional mode, elements in the integrated circuit are connected according to a desired design and to provide a desired utility for which the integrated circuit is primarily designed. In test mode, the integrated circuit is generally designed to connect various memory elements (contained in the integrated circuit) such as flip-flops in a sequence referred to as a “scan chain” (i.e., the output of one element is connected as an input to the next element). The first element in the scan chain is generally designed to receive the input bits and the last element of the scan chain is designed to scan out the results of evaluation, as described below.
In a typical scan test scenario, a number of bits in a particular pattern of zeros and ones (scan vector) are sequentially (one bit at every clock cycle) loaded (scanned in) into scan chain through the first element. The number of bits contained in the scan vector generally equals the number of memory elements in a corresponding scan chain. Once a scan chain is loaded with a scan vector, the elements (generally the combinatorial logic) in the integrated circuit are evaluated based on the scanned in bits. The flip-flops are designed to latch the results of the evaluation, and the bits latched in the scan chain are sequentially scanned out (one bit at every clock cycle) through the last element in the scan chain. The received scan out is compared with an expected scan out corresponding to the scan vector to determine the various faults within the integrated circuit. Multiple scan chains are present, particularly in very large scale integrated circuits. Each scan chain covers a corresponding portion of the integrated circuit, and thus may need to be tested with a corresponding set of scan vectors. Accordingly, when a scan chain is loaded and tested with a scan vector, a desired controllability (of the internal logic of the portion being tested) and observability (visibility of the corresponding accuracy of operation) of the corresponding portion is obtained.
In general, such tests need to be performed meeting at least some of several requirements. Some of such requirements include minimizing the testing time, reducing power dissipation during test time, etc. Reducing the test time generally leads to corresponding lower costs since the usage of testing equipment (and labor type overhead) is reduced. Reduction of power dissipation is of concern since substantially more power dissipation may occur in test mode compared to functional mode, and integrated circuits may be designed with a power dissipation specification corresponding to only the functional mode.
In a SoC with multiple cores, an ideal way to practice hierarchical scan testing is to permit one test mode for each individual core where the other cores are not tested. However, due to the presence of top-level logic (glue logic) and interaction among the cores, some top-level testing is unavoidable. In the traditional divide-and-conquer scan test, the top-level testing takes the form of the so-called “daisy chain” mode or “residual scan” mode in which internal scan chains in the cores are reconfigured into top-level scan chains and the entire scan flip-flops in the design participate in testing. The residual scan mode is expensive in terms of test application time and test power and wipes out the benefits achieved by hierarchical scan. This is also the case for hierarchical scan test compression; while core internal test patterns may be compressed and lead to reduction in test application time, no compression may be possible for the full residual test mode. As a result, the overall test time reduction and scan pattern volume reduction may be small, even though dramatic improvements in test time and scan data volume are possible in individual core internal test modes. Hence, the problem of bringing down the negative impact of the full residual test mode is addressed. The problem is more challenging when the cores are unwrapped i.e., do not have bounding chains. Most of the existing work on test time reduction assumes that the cores have test wrappers. Reducing the scan test time and scan test power for unwrapped cores such as Application Specific Integrated Circuits (ASICs) remains a large problem.